Since liquid crystal display (LCD) devices have low power consumption and a high mobility, they have been touted as the next generation display device. Among LCD devices, active matrix type LCD devices, which have high resolution and are effective at displaying moving images, are widely used.
In general, LCD devices are fabricated through an array substrate process, a color filter substrate process, and a cell process. In the array substrate process, a thin film transistor (TFT) and a pixel electrode may be formed on a first substrate. In the color filter substrate process, a color filter and a common electrode may be formed on a second substrate. In the cell process, a liquid crystal layer is formed between the first and second substrates.
An LCD device is shown in detail in FIG. 1A. FIG. 1A is an exploded perspective view of a conventional LCD device. As shown, the first and, second substrates 12 and 22 face each other, and the liquid crystal layer 30 is interposed therebetween. The first substrate 12 includes a plurality of gate lines 14, a plurality of data lines 16, a plurality of TFTs (“Tr”), a plurality of pixel electrodes 18, and so on. The gate line 14 and the data line 16 cross each other such that a region formed between the gate and data lines 14 and 16 is defined as a pixel region (“P”). The TFT “Tr” is formed at a crossing portion between the gate and data lines 14 and 16, and the pixel electrode 18 is formed in the pixel region “P” and connected to the TFT “Tr.”
The second substrate 22 includes a black matrix 25, the color filter 26, and the common electrode 28, and so on. The black matrix 25 has a lattice shape to cover a non-display region, such as the gate line 14, the data line 16, the TFT “Tr,” and so on. The color filter 26 is formed within the black matrix 25 and corresponds to the pixel region “P.” The color filter 26 includes red, green, and blue colors. The common electrode 28 is formed on the black matrix 25 and the color filter 26 over an entire surface of the second substrate 22. The common electrode 28 may be made of transparent material.
Though not shown, a sealant is formed between edges of the first and second substrates 12 and 22. First and second alignment layers may be formed between the first substrate 12 and the liquid crystal layer 30 and between the second substrate 22 and the liquid crystal layer 30, and a polarizing plate may be formed on an outer surface of the first substrate 12 or the second substrate 22. Also, a backlight assembly below the first substrate 12 supplies light into the liquid crystal layer 30. The liquid crystal layer 30 is driven by an electric field between the pixel electrode 18 and the common electrode 28 such that the LCD device displays images.
In a conventional method of fabricating the LCD device, and more particularly, in a method of fabricating the array substrate, a mask process is used for patterning the data and gate lines, the pixel electrode, and so on. Since the mask process includes many steps, such as a step of coating a photoresist, a step of developing, a step of etching, a step of stripping, and so on, a production time increases and production yield decreases. Accordingly, a new method of fabricating the array substrate for the LCD device, referred to as 4 mask process, has been suggested to resolve these problems. The conventional method of fabricating the array substrate includes 5 mask processes.
FIGS. 2A to 2C show cross-sectional views of processes of fabricating the pixel region of the array substrate using the 4 mask process.
As shown in FIG. 2A, a gate electrode 55, the gate line (not shown), a gate insulating layer 57, the data line 65, an active layer 60a of intrinsic amorphous silicon, an ohmic contact pattern 61 of impurity-doped amorphous silicon, a source-drain pattern 66, a passivation layer 75, and a transparent conductive material layer 78 are formed on the first substrate 50.
The gate electrode 55 and the gate line (not shown) are formed on the first substrate 50 in the switching region TrA by depositing and patterning a first metal layer (not shown) using a first mask (not shown). The gate electrode 55 may be extended and may protrude from the gate line (not shown). The gate insulating layer 57 is formed on the first substrate including the gate electrode 55 and the gate line (not shown). Though not shown, an intrinsic amorphous silicon layer, an impurity-doped amorphous silicon layer, and a second metal layer are formed on the gate insulating layer 57. And then, the active layer 60a, the ohmic contact pattern 61, and the source-drain pattern 66 are formed by sequentially patterning the intrinsic amorphous silicon layer, the impurity-doped amorphous silicon layer, and the second metal layer using a second mask (not shown). At the same time, the data line 65 is formed from the second metal layer. The gate insulating layer 57, an intrinsic amorphous silicon pattern 62a, and an impurity-doped amorphous silicon pattern 62b are formed between the data line 65 and the first substrate 50.
Next, the passivation layer 75 having a drain contact hole 76 is formed on the source-drain pattern 66 by depositing and patterning an inorganic material layer (not shown) by using a third mask (not shown). The drain contact hole 76 partially exposes the source-drain pattern 66. The transparent conductive material layer 78 is formed on the passivation layer 75 and contacts the source-drain pattern 66 through the drain contact hole 76. Then, a photoresist (PR) layer 85 having a first height h1 from the first substrate 50 is formed on the transparent conductive metal layer 78, and a fourth mask 91 is disposed over the PR layer 85. The fourth mask 91 has a transmissive area “TA,” a blocking area “BA,” and a half-transmissive area “HTA.” The half-transmissive area “HTA” has a transmittance less than the transmissive area TA and greater than the blocking area “BA.” Then, the PR layer 85 is exposed by light through the fourth mask 91.
As shown in FIG. 2B, first and second PR patterns 85a and 85b are formed on the transparent conductive metal pattern 78 by developing the PR layer 85. The first PR pattern 85a corresponds to the blocking area BA to have the first height hi from the first substrate 50, and the second PR pattern 85b corresponds to the half-transmissive area “HTA” to have the second height h2 from the first substrate 50, which is less than the first height h1. The PR layer 85 corresponding to the transmissive area TA is completely removed such that the transparent conductive material pattern 78 corresponding to the gate electrode 55 is exposed between the second PR patterns 85b. 
Since the transparent conductive material layer 78 has a step difference, the second PR pattern 85b has first, second, and third thicknesses t1, t2, and t3 from the transparent conductive metal layer 78. The second thickness t2 is greater than the first thickness t1 and less than the third thickness t3. The second PR pattern 85b in a first region A1 has the first thickness t1 due to the highest step from the gate electrode 55, the active layer 60a, the ohmic contact pattern 61, and the source-drain pattern 66. The second PR pattern 85b in a second region A2 has the second thickness t2 due to a middle step without the gate electrode 55, and the second pattern 85b in a third region A3 has the third thickness t3 due to the lowest step without the gate electrode 55, the active layer 60a, the ohmic contact pattern 61, and the source-drain pattern 66.
As shown in FIG. 2C, the transparent conductive material layer 78 exposed between the second PR patterns 85b is removed. Sequentially, the source-drain pattern 66 and the ohmic contact pattern 61 exposed by removing the transparent conductive material layer 78 are removed such that a source electrode 67, a drain electrode 69, and an ohmic contact layer 60b are formed. The ohmic contact layer 60b and the active layer 60a are as a semiconductor layer 60. Next, the second PR pattern 85b is removed from the transparent conductive metal pattern 78 by ashing. At the same time, the first PR pattern 85a is partially removed. The ashing should be perfectly performed to expose the transparent conductive metal layer 78 until the second PR pattern 85b in the third region A3 is perfectly removed.
In this case, before the ashing is finished, the second PR pattern 85b having the first thickness t1 or/and the second thickness t2 is exposed. Accordingly, since the ashing time increases as much as an ashing time of different thickness between the first and second thickness t1 and t2 or between the second and third thickness t2 and t3, the production time of the array substrate increases.